1. Field of the Invention
This invention relates to the field of processors and, more particularly, to prefetching mechanisms within processors.
2. Description of the Related Art
Superscalar processors achieve high performance by executing multiple instructions per clock cycle and by choosing the shortest possible clock cycle consistent with the design. On the other hand, superpipelined processor designs divide instruction execution into a large number of subtasks which can be performed quickly, and assign pipeline stages to each subtask. By overlapping the execution of many instructions within the pipeline, superpipelined processors attempt to achieve high performance.
Superscalar processors demand low memory latency due to the number of instructions attempting concurrent execution and due to the increasing clock frequency (i.e. shortening clock cycle) employed by the superscalar processors. Many of the instructions include memory operations to fetch (read) and update (write) memory operands. The memory operands must be fetched from or conveyed to memory, and each instruction must originally be fetched from memory as well. Similarly, superpipelined processors demand low memory latency because of the high clock frequency employed by these processors and the attempt to begin execution of a new instruction each clock cycle. It is noted that a given processor design may employ both superscalar and superpipelined techniques in an attempt to achieve the highest possible performance characteristics.
Processors are often configured into computer systems which have a relatively large, relatively slow main memory. Typically, multiple dynamic random access memory (DRAM) modules comprise the main memory system. The large main memory provides storage for a large number of instructions and/or large amount of data for use by the processor, providing faster access to the instructions and/or data than may be achieved from a disk storage, for example. However, the access times of modern DRAMs are significantly longer than the clock cycle length of modern processors. The memory access time for each set of bytes being transferred to the processor is therefore long. Accordingly, the main memory system is not a low latency system. Processor performance may suffer due to high memory latency.
In order to allow low latency memory access (thereby increasing the instruction execution efficiency and ultimately processor performance), computer systems typically employ one or more caches to store the most recently accessed data and instructions. Additionally, the processor may employ caches internally. A relatively small number of clock cycles may be required to access data stored in a cache, as opposed to a relatively larger number of clock cycles required to access the main memory.
Low memory latency may be achieved in a computer system if the cache hit rates of the caches employed therein are high. An access is a hit in a cache if the requested data is present within the cache when the access is attempted. On the other hand, an access is a miss in a cache if the requested data is absent from the cache when the access is attempted. Cache hits are provided to the processor in a small number of clock cycles, allowing subsequent accesses to occur more quickly as well and thereby decreasing the effective memory latency. Cache misses require the access to receive data from the main memory, thereby increasing the effective memory latency.
In order to increase cache hit rates, computer systems may employ prefetching to "guess" which data will be requested by the processor in the future. The term prefetch, as used herein, refers to transferring data (e.g. a cache line) into a cache prior to a request for the data being received by the cache in direct response to executing an instruction (either speculatively or non-speculatively). A request is in direct response to executing the instruction if the definition of the instruction according to the instruction set architecture employed by the processor includes the request for the data. A "cache line" is a contiguous block of data which is the smallest unit for which a cache allocates and deallocates storage. If the prefetched data is later accessed by the processor, then the cache hit rate may be increased due to transferring the prefetched data into the cache before the data is requested.
Unfortunately, prefetching can consume memory bandwidth at an inopportune time with respect to the occurrence of non-speculative memory operations. For example, a prefetch memory operation may be initiated just slightly prior to the initiation of a non-prefetch memory operation. As the prefetch memory operation is occupying the memory system already, the latency of the non-prefetch memory operation is increased by the amount of time the memory system is occupied with the prefetch request. Particularly if the prefetch is incorrect (i.e. the prefetched data is not used later by the requester), the increased latency may decrease performance of the processor (and the overall computer system).